EurekAlert!

First 2D semiconductor FPGA achieves wafer-scale integration

The global integrated circuit (IC) industry is confronting the physical limitations of Moore's Law. Atomic-layer-thick two-dimensional (2D) semiconductors, such as Molybdenum Disulfide (MoS2), are ...
Reuters

IBM says conventional AMD chips can run quantum computing error correction algorithm

SAN FRANCISCO, Oct 24 (Reuters) - IBM (IBM.N), opens new tab said on Friday it can run a key quantum computing error correction algorithm on commonly available chips ...
UMass Lowell

Master's Thesis Defense in Electrical and Computer Engineering: Sriram Krishnamoorthy 8/1

Advisor: Orlando Arias, Assistant Professor, Electrical and Computer Engineering, University of Massachusetts Lowell Kavitha Chandra, Ph.D., Electrical and Computer Engineering Department, University ...
Hackaday

Vintage Intel 8080 Runs On A Modern FPGA

If you’re into retro CPUs and don’t shy away from wiring old-school voltages, [Mark]’s latest Intel 8080 build will surely spark your enthusiasm. [Mark] has built a full system board for the venerable ...
The Motley Fool

Intel Dumps Altera at a Huge Loss

Intel is selling a 51% stake in the FPGA company at a large loss. The deal simplifies Intel's operations and raises cash. Intel will still benefit from Altera's success with a 49% minority stake.
Business Wire

Aldec Launches HES-DVM Proto ‘Cloud Edition’ - Giving Engineers Easier Access to FPGA-based ASIC & SoC Prototyping

HENDERSON, Nev.--(BUSINESS WIRE)--Aldec, Inc., a pioneer in mixed HDL language simulation and hardware-assisted verification for FPGA and ASIC designs, has launched HES-DVM Proto Cloud Edition (CE).
IEEE

Partitioning FPGA-Optimized Systolic Arrays for Fun and Profit

Abstract: We can improve the inference throughput of deep convolutional networks mapped to FPGA-optimized systolic arrays, at the expense of latency, with array partitioning and layer pipelining.