# SW Build 6140274 on Thu May 22 00:12:29 MDT 2025 # IP Build 6138677 on Thu May 22 03:10:11 MDT 2025 # SharedData Build 6139179 on Tue May 20 17:58:58 MDT 2025 # Start of session at: Wed Oct 22 17:33 ...
RTL design and functional verification of a 32-bit ALU using Verilog HDL. Supports arithmetic, logical, and shift operations with corner-case handling such as divide-by-zero, underflow, and tri-state ...
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