Abstract: The AMD Pynq ecosystem fails to provide a seamless way to easily validate functional correctness of RTL designs when part of the application logic runs in Python on the ARM (or x86) host CPU ...
A fully synthesizable UART (Universal Asynchronous Receiver-Transmitter) core designed for FPGA implementation. Tested on Altera MAX 10 FPGA, this project demonstrates a modern digital design workflow ...
Parses live-format NASDAQ ITCH 5.0 binary data, extracts trading features, and runs single-sample inference through a pipelined bfloat16 dot-product engine — all in under 5 cycles at 300 MHz.
Some results have been hidden because they may be inaccessible to you
Show inaccessible results