EDN

JTAG 101 – Part 2: A review of on-chip debug types

Several processor vendors have extended JTAG software debug, often to make it faster, or to add hardware trace capabilities. The NEXUS consortium for example defines an auxiliary port containing a ...
EDN

JTAG 101 – Part 1: Overview and On-Chip Debug Methods

JTAG (jay-tag) is one of the engineering acronyms that has been transformed into a noun, although arguably it is not so popular as RAM, or CPU. IEEE Std 1149.1-1990 IEEE Standard Test Access Port and ...
CU Independent

Bug Tracking Tools vs Debugging: What You Need

Often, people ask questions about the differences between debugging and bug tracking. These two seem like they should be ...
Semiconductor Engineering

Understanding Scandump: A Key Silicon Debugging Technique

Scandump is an advanced silicon debugging technique that ingeniously repurposes DFT (Design For Testability) scan chains for functional debugging. This method allows for the extraction of states from ...
Electronic Design

Debugging Optimized Code

If you have ever tried to debug optimized code, you probably realized that it can be a frustrating experience. Without optimizations, your debugger is a reliable assistant, precisely following every ...
Electronic Design

Hardware Emulation for Software Validation (Part 2): Hybrid Emulation and Trace-Based Debug

Editor’s Note: Lauro Rizzatti went to Russell Klein, director of engineering at Mentor Graphics and a hardware emulation expert, to learn more about hybrid emulation. This column is co-authored by the ...