Phase-Locked Loops (PLLs) are commonly used to perform a variety of clock processing tasks, such as clock frequency multiplication and clock deskewing. PLLs, like many other analog IP macros, come ...

Editor's Note: Although the primary target market for the 86100CU-400 application presented below is for ASIC/SoC designs, I'm assured by the folks at Agilent that this application is also applicable ...

To support the data rates of 64Gbps and beyond, we believe a fundamental architectural shift is necessary. This article outlines our R&D team's upcoming PLL suitable for high-speed SerDes having ultra ...

The high-speed serial interface signals supporting today's computer and communications systems are too fast for most general-purpose test equipment. For example, PCI Express operates at a 2.5-GHz bit ...

Behavioral modeling and simulation of a PLL based integer n frequency synthesizer has been illustrated in this paper. The synthesizer generates a signal of 5.15-5.25GHz in the UNII (Unlicensed ...